It is well known in the art of printed circuit board design to utilize capacitors to smooth the effects of sporadic current peaks and noise typical of electronic circuitry. Theoretically, a capacitor has the characteristic of maintaining a substantially constant voltage while absorbing applied current changes, which is a typically important function in computer circuit design where current surges and peaks due to noise and the like must be smoothed to prevent interference with signal generation. In other words, capacitors are used to stabilize the supply voltage by compensating for abrupt current changes.
However, due to the application of current across a capacitor, the capacitor generates an inductance called "parasitic" inductance. And, just as in the case of an inductor, such parasitic inductance can limit the rate of current change across the capacitor and thus cause the voltage to drop in spite of the presence of the capacitor. Further, such parasitic inductance can change the RF impedance characteristics of capacitors making them more complex elements in RF (radio frequency) applications, which makes design more complicated and performance objectives more difficult to achieve.
Methods have been tried to reduce parasitic capacitor inductance. One method is to reduce the length of conductor traces extending between the capacitor terminal and the pad of a via. Another suggestion is the widening of capacitors and traces and shortening or eliminating traces from the capacitor pads to vias. However, there is a lower limit on capacitor lengths. For example, if a capacitor is too short, there is not enough space between the metalized contacts located at the ends of the capacitors and solder bridging to the metalized contacts or terminals becomes a problem. Capacitor shortening can also be difficult where board fabrication processes set the minimum space between vias, which dictates the minimum total length for the capacitor and the mounting structure combined. Increasing capacitor width at minimum length increases space occupied by the capacitor which diminishes available board space. In addition, there is a limit to the ratio of width to length in capacitor fabrication. Even with maximized capacitor width, within the practical range of capacitor and trace widths, inductance can only be reduced 30-40%.